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SV51011
2014.01.10
Error Detection Registers
9-7
Name
User update register
User shift register
JTAG fault injection register
Fault injection register
Width (Bits)
67
67
46
46
Description
This register is automatically updated with the contents of
the EMR one clock cycle after the contents of this register
are validated. The user update register includes a clock
enable, which must be asserted before its contents are written
to the user shift register. This requirement ensures that the
user update register is not overwritten when its contents are
being read by the user shift register.
This register allows user logic to access the contents of the
user update register via the core interface.
You can use this register with the EDERROR_INJECT JTAG
instruction to inject errors in the bitstream. Table 9-7 lists
the fields in this register.
This register is updated with the contents of the JTAG fault
injection register.
Figure 9-4: Error Message Register Map
MSB
LSB
Syndrome
32 bits
Frame Address
16 bits
Double Word
Location
10 bits
Byte Offset
2 bits
Bit Offset
3 bits
Error Type
4 bits
Table 9-6: Error Type in EMR
The following table lists the possible error types reported in the error type field in the EMR.
Bit 3
Error Type
Bit 2 Bit 1
Bit 0
Description
0
0
0
1
0
0
0
1
0
0
1
1
0
1
0
1
No CRC error.
Location of a single-bit error is identified.
Location of a double-adjacent error is identified.
Error types other than single-bit and double-adjacent errors.
Table 9-7: JTAG Fault Injection Register Map
Field Name
Error Byte
Value
Byte Location
SEU Mitigation for Stratix V Devices
Send Feedback
Bit Range
31:0
41:32
Description
Contains the location of the bit error that
corresponds to the error injection type to this
field.
Contains the location of the injected error in
the first data frame.
Altera Corporation
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